GENERAL DESCRIPTION：

The ADAU1701 is a complete single-chip audio system with a28-/56-bit audio DSP, ADCs, DACs, and microcontroller-likecontrol interfaces. Signal processing includes equalization, crossover, bass enhancement, multiband dynamics processing, delaycompensation, speaker compensation, and stereo image widening.This processing can be used to compensate for real-worldlimitations of speakers, amplifiers, and listening environments,providing dramatic improvements in perceived audio quality.Its signal processing is comparable to that found in high endstudio equipment. Most processing is done in full 56-bit, doubleprecision mode, resulting in very good low level signal performance. The ADAU1701 is a fully programmable DSP. The easy touse SigmaStudio™ software allows the user to graphically configurea custom signal processing flow using blocks such as biquad filters,dynamics processors, level controls, and GPIO interface controls.ADAU1701 programs can be loaded on power-up either from aserial EEPROM through its own self-boot mechanism or froman external microcontroller. On power-down, the current stateof the parameters can be written back to the EEPROM from theADAU1701 to be recalled the next time the program is run.Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analoginput to analog output dynamic. Each ADC has a THD + N of−83 dB, and each DAC has a THD + N of −90 dB. Digital inputand output ports allow a glueless connection to additionalADCs and DACs. The ADAU1701 communicates through anI2C® bus or a 4-wire SPI port.

FEATURES：

28-/56-bit, 50 MIPS digital audio processor

2 ADCs: SNR of 100 dB, THD + N of −83 dB

4 DACs: SNR of 104 dB, THD + N of −90 dB

Complete standalone operation

Self-boot from serial EEPROM

Auxiliary ADC with 4-input mux for analog control

GPIOs for digital controls and outputs

Fully programmable with SigmaStudio graphical tool

28-bit × 28-bit multiplier with 56-bit accumulator for fulldouble-precision processing

Clock oscillator for generating a master clock from crystal

PLL for generating master clock from 64 × fS, 256 × fS,384 × fS, or 512 × fS clocks

Flexible serial data input/output ports with I2S-compatible,left-justified, right-justified, and TDM modes

Sampling rates of up to 192 kHz are supported

On-chip voltage regulator for compatibility with 3.3V systems

48-lead, plastic LQFP

APPLICATIONS：

Multimedia speaker systems

MP3 player speaker docks

Automotive head units

Minicomponent stereos

Digital televisions

Studio monitors

Speaker crossovers

Musical instrument effects processorsIn-seat sound systems (aircraft/motor coaches)