Overview：

This chapter gives an overview of the 4Gbit DDR3L SDRAM component product and describes its main characteristics.

Features：

The 4Gbit DDR3L SDRAM offers the following keyfeatures:

• VDD,=VDDQ=1.35V(1.283V-1.45V)

。 Backward compatible to VDD=VDDQ=1.5 V ±0.075V)

-Supports DDR3L devices to be backward compatible in1.5V applications

。Data rate :1600Mbps/1866Mbps/2133Mbps

。Differential bidirectional data strobe

。 8n-bit prefetcharchitecture

。Differential clock inputs (CK, CKB)

。8 internal banks

。Nominal and dynamic on-die termination (ODT) for data,strobe, and mask signals

。Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (viathe mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self-refresh mode

• TC of 0°C to + 95°C– 64ms, 8192-cycle refresh at 0°C to +85°C– 32ms at +85°C to +95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multi-purpose register

• Output driver calibration

Options：

• Configuration

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x8

– 78-ball (10.6mm x 7.5mm)

• FBGA package (Pb-free) – x16

– 96-ball (13.5mm x 7.5mm)

• Timing – cycle time

– 938ps @ CL = 14 (DDR3-2133)

– 1.07ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

• Operating temperature

– Commercial, (0°C ≤TC ≤ +95°C)

– Industrial, (-40°C ≤TC ≤ +95°C)