General Description：

The ECP5™/ECP5-5G™ family of FPGA devices isoptimized to deliver high performance features such asan enhanced DSP architecture, high speed SERDES(Serializer/Deserializer), and high speed sourcesynchronous interfaces, in an economical FPGA fabric.This combination is achieved through advances indevice architecture and the use of 40 nm technologymaking the devices suitable for high-volume, highspeed, and low-cost applications.The ECP5/ECP5-5G device family covers look-up-table(LUT) capacity to 84K logic elements and supports upto 365 user I/O. The ECP5/ECP5-5G device family alsooffers up to 156 18 x 18 multipliers and a wide range ofparallel I/O standards.The ECP5/ECP5-5G FPGA fabric is optimized highperformance with low power and low cost in mind. TheECP5/ ECP5-5G devices utilize reconfigurable SRAMlogic technology and provide popular building blockssuch as LUT-based logic, distributed and embeddedmemory, Phase-Locked Loops (PLLs), Delay-LockedLoops (DLLs), pre-engineered source synchronous I/Osupport, enhanced sysDSP slices and advancedconfiguration support, including encryption anddual-boot capabilities.The pre-engineered source synchronous logicimplemented in the ECP5/ECP5-5G device familysupports a broad range of interface standardsincluding DDR2/3, LPDDR2/3, XGMII, and 7:1 LVDS.The ECP5/ECP5-5G device family also features highspeed SERDES with dedicated Physical Coding Sublayer(PCS) functions. High jitter tolerance and low transmitjitter allow the SERDES plus PCS blocks to beconfigured to support an array of popular dataprotocols including PCI Express, Ethernet (XAUI, GbE,and SGMII) and CPRI. Transmit De-emphasis withpre- and post-cursors, and Receive Equalizationsettings make the SERDES suitable for transmission andreception over various forms of media.The ECP5/ECP5-5G devices also provide flexible,reliable and secure configuration options, such asdual-boot capability, bit-stream encryption, andTransFR field upgrade features.ECP5-5G family devices have made some enhancementin the SERDES compared to ECP5UM devices. Theseenhancements increase the performance of theSERDES to up to 5 Gb/s data rate.The ECP5-5G family devices are pin-to-pin compatiblewith the ECP5UM devices. These allows a migrationpath for you to port designs from ECP5UM to ECP5-5Gdevices to get higher performance.

The Lattice Diamond™ design software allows largecomplex designs to be efficiently implemented usingthe ECP5/ECP5-5G FPGA family. Synthesis librarysupport for ECP5/ECP5-5G devices is available forpopular logic synthesis tools. The Diamond tools usethe synthesis tool output along with the constraintsfrom its floor planning tools to place and route thedesign in the ECP5/ECP5-5G device. The tools extractthe timing from the routing and back-annotate it intothe design for timing verification.Lattice provides many pre-engineered IP (IntellectualProperty) modules for the ECP5/ECP5-5G family. Byusing these configurable soft core IPs as standardizedblocks, designers are free to concentrate on the uniqueaspects of their design, increasing their productivity.

Features：

 Higher Logic Density for Increased SystemIntegration

 12K to 84K LUTs

 197 to 365 user programmable I/O

 Embedded SERDES

 270 Mb/s, up to 3.2 Gb/s, SERDES interface(ECP5)

 270 Mb/s, up to 5.0 Gb/s, SERDES interface(ECP5-5G)

 Supports eDP in RDR (1.62 Gb/s) and HDR

 (2.7 Gb/s)

 Up to four channels per device: PCI Express,Ethernet (1GbE, SGMII, XAUI), and CPRI

 sysDSP™

 Fully cascadable slice architecture

 12 to 160 slices for high performance multiplyand accumulate

 Powerful 54-bit ALU operations

 Time Division Multiplexing MAC Sharing

 Rounding and truncation

 Each slice supports

 Half 36 x 36, two 18 x 18 or four9 x 9 multipliers

 Advanced 18 x 36 MAC and18 x 18 Multiply-Multiply-Accumulate(MMAC) operations

 Flexible Memory Resources

 Up to 3.744 Mb sysMEM™ Embedded Block

 RAM (EBR)

 194K to 669K bits distributed RAM

 sysCLOCK Analog PLLs and DLLs

 Four DLLs and four PLLs in LFE5-45 andLFE5-85; two DLLs and two PLLs in LFE5-25and LFE5-12

 Pre-Engineered Source Synchronous I/O

 DDR registers in I/O cells

 Dedicated read/write levelling functionality

 Dedicated gearing logic

 Source synchronous standards support

 ADC/DAC, 7:1 LVDS, XGMII

 High Speed ADC/DAC devices

 Dedicated DDR2/DDR3 and LPDDR2/LPDDR3memory support with DQS logic, up to800 Mb/s data-rate

 Programmable sysI/O™ Buffer Supports WideRange of Interfaces

 On-chip termination

 LVTTL and LVCMOS 33/25/18/15/12

 SSTL 18/15 I, II

 HSUL12

 LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

 subLVDS and SLVS, SoftIP MIPI D-PHYreceiver/transmitter interfaces

 Flexible Device Configuration

 Shared bank for configuration I/O

 SPI boot flash interface

 Dual-boot images supported

 Slave SPI

 TransFR™ I/O for simple field updates

 Single Event Upset (SEU) Mitigation Support

 Soft Error Detect – Embedded hard macro

 Soft Error Correction – Without stopping useroperation

 Soft Error Injection – Emulate SEU event todebug system error handling

 System Level Support

 IEEE 1149.1 and IEEE 1532 compliant

 Reveal Logic Analyzer

 On-chip oscillator for initialization and generaluse

 V core power supply for ECP5, 1.2 V corepower supply for ECP5UM5G